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respond read, write, or seek command. DRDY=0 indicates that read , write and seek are negated. A command execution shall be interrupted if Not-Ready condition occurs during a command execution and will be reset until the next command whether the drive condition is Ready or Not Ready. Error bit is set on this occasion and will be reset just after power on and set again after the drive begins revolving at normal speed and gets ready to receive a command. Bit 5 DF (Device Fault) -- DF=1 indicates that the drive has detected a fault condition during the execution of a Read Write commands; read, write, and seek commands are negated and Error bit is set. DF is set to 1 until the next command, whether the device is in fault condition or not. Bit 4 DSC3 (Drive Seek Complete) DSC³= 1 indicates that a seek operation has been completed. DSC³ is set to 0 when a command accompanied by a seek operation begins. If a seek is not complete, a command is terminated and this bit is not changed until the Status Register is read by the host . This bit remains reset immediately after power on until the drive starts revolving at a nominal speed and gets ready to receive command. Bit 3 DRQ (Data Request) -- DRQ=1 indicates that the sector buffer requires 1 sector of data during a Read or Write command. Bit 2 CORR (Corrected Data) -- CORR=1 indicates that the data read from the disk had an error but was successfully corrected by the read retry. This bit is always set to 0 and does not interrupt multi-sector operations. Bit 1 IDX (Index) -- This bit is a pulse signal set to 1 per revolution of the disk. Intervals of the signal may vary during read / write operation. Therefore, the host shouldn t use IDX for timing purposes. Bit 0 ERR (Error) -- ERR = 1 indicates that an error occurred during execution of the previous command . The cause of the error is reported on the other bit or in the error register. The error bit can be reset by the next command from the controller. When this bit is set , a multi-sector operation is negated. 3 ATA-2 Notes: Prior to ATA-2 standard, this bit indicated that the device was on track. This bit may be used for other purposes in future standards. For compatibility the drive supports this bit as ATA-1 specifies. User is recommended not to use this bit. Copyright © 2002 Toshiba corporation. All rights reserved. - 555 - 360042730 10.7.10 Command Register - CS0 DA2-DA0 : 7 Write only The command register accepts commands for the drive to perform fixed disk operations. Commands are executed when the TASK FILE is loaded and the command register is written and only when: The status is not busy (BSY is inactive). and DRDY (drive ready) is active. Any code NOT defined in the following list causes an Aborted Command error. Interrupt request (INTRQ) is reset when a command is written. The following are acceptable commands to the command register. Copyright ©2002 Toshiba corporation. All rights reserved. - 556 - 360042730 Table 10.7-2 Command Code Command Code Command Name Hex Value PARAMETERS USED SC SN CY DRV HD FT Nop 00H X X X O X X Recalibrate 1xH X X X O X X Read Sector(s) 20/21H O O O O O X Read Long 22/23H O O O O O X Write Sector(s) 30/31H O O O O O X Write Long 32/33H O O O O O X Write Verify 3CH O O O O O X Read Verify Sector(s) 40/41H O O O O O X Format Track 50H X X O O O X Seek 7xH X X O O O X Execute Diagnostics 90H X X X O X X Initialize Device Parameters 91H O X X O O X SMART B0H X X O O X O Read Multiple C4H O O O O O X Write Multiple C5H O O O O O X Set Multiple Mode C6H O X X O X X Read DMA C8/C9H O O O O O X Write DMA CA/CBH O O O O O X Power Control Stand-by Immediate E0 / 94H O X X O X X Idle Immediate E1 / 95H O X X O X X Stand-by E2 / 96H O X X O X X Idle E3 / 97H O X X O X X Check Power Mode E5 / 98H O X X O X X Sleep E6 / 99H O X X O X X Read Buffer E4H X X X O X X Flush Cache E7H X X X O X X Write Buffer E8H X X X O X X Identify Device ECH X X X O X X Set Features EFH X X X O X O Security Set Password F1H X X X O X X Unlock F2H X X X O X X Erase Prepare F3H X X X O X X Erase Unit F4H X X X O X X Freeze F5H X X X O X X Disable Password F6H X X X O X X Read Native Max Address F8H X X X O X X Set Max Address F9H O O O O O X Note: O and X are defined as follows. O = Must contain valid information for this command. X = Don't care for this command. L = 0 indicates normal read/ write. 1 indicates Long command ( ECC Byte transfer ). Parameters are defined as follows. SC = SECTOR COUNT register. SN = SECTOR NUMBER register. CY = CYLINDER LOW and CYLINDER HIGH register. DRV = DRIVE SELECT bit (bit 4 in DRIVE/HEAD register) HD = HEAD SELECT bits (bit 3-0 in DRIVE/HEAD register) FT = FEATURES register (WRITE PRECOMPENSATION register) Copyright © 2002 Toshiba corporation. All rights reserved. - 557 - 360042730 10.7.11 Alternate Status Register - CS1 DA2-DA0 : 6 Read only This register contains the same information as the status register in the Task File. The only difference is that this register being read does not imply interrupt acknowledge or doesn t reset a pending interrupt. See the description of status resister for definitions of the bit in this register. 10.7.12 Device Control Register - CS1 DA2-DA0 : 6 Write only This register contains the following two control bits. ---- ---- ---- ---- 1 SRST - IEN ---- Bit 7-4 not used Bit 3 Reserved (recommended to set 1) Bit 2 SRST (Soft Reset) -- SRST= 1 indicates that the drive is held reset and sets BSY bit in Status register. All internal registers are reset as shown in Table 10.12-1 . If two drives are daisy chained on the interface, this bit will reset both drives simultaneously , regardless of the selection by Device address bit in DEVICE/HEAD register. Bit 1 - IEN (Interrupt Enable) -- When -IEN = 0, and the drive is selected by Drive select bit in DEVICE/HEAD register, the drive interrupt to the host is enabled. When this bit is set, the - INTRQ pin will be in a high impedance state, whether a pending interrupt is found or not. Bit 0 not used 10.7.13 Device Address register4 - CS1 DA2-DA0 : 7 read only The device address register is a read-only register used for diagnostic purposes. The followings are definitions of bits for this register: RSVD - WTG - HS3 - HS2 - HS1 - HS0 - DS1 - DS0 Bit 7 Reserved -- high impedance Bit 6 - WTG (Write Gate) -- This bit is active when a Write to the disk is in progress. Bit 5 - Bit 2 - HS3 to - HS0 (Head Select bits) -- Bit 5 through 2 are one's complement of the binary coded address of currently selected head which is shown by Head Select bit in SDH register. Bit 1 - DS1 (Drive Select 1) -- -DS1=0, when SLAVE drive is selected and active. Bit 0 - DS0 (Drive Select 0) -- -DS0=0, when single mode or MASTER drive in Master/Slave mode is selected and active. Note) The following facts should be taken into consideration when this resister is in use. -WG reflects actual write gate in the drive, however, because of address transition or cache operation, there is no direct connection with the data transferred between host and drive. -HEAD SELECT represents one s complement of the binary coded address of currently selected head, but does not show actual selection of the head. 4 ATA-2 Notes: This register is obsolete. A device is not supposed to respond to a read of this address. If a device does [ Pobierz caÅ‚ość w formacie PDF ] |